Conventional processors are configured to support a variety of instructions. In many instances, processor circuitry is configured to perform particular instructions. Instructions are often handled sequentially using specially configured subcircuitry. In one instance, a particular type of instruction, the branch instruction, allows the flow of execution of a program to change by performing a jump to a non-sequential instruction at a branch target address. Specialized circuitry is often provided to calculate addresses that are the target of the jump operations for branch instructions.
However, mechanisms for efficiently performing calculations for different types of instructions are limited. In one example, specialized subcircuitry is configured to calculate multi-byte branch aligned target addresses. However, the specialized subcircuitry is often not reused for other types of instructions.
Mechanisms for efficiently optimizing processor cores are limited. It is therefore desirable to provide improved methods and apparatus for optimizing implementation of processors and processor circuitry. In some instances, alignment restrictions can be relaxed to allow further processor optimization.